Senior RTL Design Engineer

Hi All, Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5 Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus. 3. Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of …