Senior Digital Verification Engineer – ASIC/FPGA

SpaceX is seeking a Principal Design Verification Engineer (Silicon Engineering) to lead digital ASIC/FPGA verification for Starlink and SpaceX hardware platforms. You will work with cross-disciplinary teams to verify complex digital designs, from block-level tests to full-system validation, enabling robust satellite and ground infrastructures. We expect a strong background in verification methodologies (UVM/OVM/VMM), extensive Python scripting, and hands-on RTL experience. J-18808-Ljbffr